Quantum Information & Computation
Volume 25, Issue 5
RESEARCH ARTICLE Open access

A Novel and Ultra-Efficient Design of Reversible Quantum Vedic Multiplier

Mojtaba Noorallahzadeh, Mohammad Mosleh

Author affiliations
  • Mojtaba Noorallahzadeh1
  • Mohammad Mosleh1
  1. Department of Computer Engineering, Dez.C., Islamic Azad University, Dezful, Iran

pp. 552-567 · 10.2478/qic-2025-0030

Read PDF View on Reference Global
On this page

Abstract

Quantum computing has attracted increased attention in recent years owing to substantial advancements in quantum algorithms and system architecture. Quantum algorithms are implemented using quantum circuits. These circuits include an intrinsic reversibility and often have a substantial Boolean component that requires synthesis. A crucial characteristic of reversible circuits is the preservation of parity. Parity-preserving logic is a category that maintains the parity of both inputs and outputs, facilitating the detection of permanent and transient errors. Multiplier circuits are essential components in digital computing systems, playing a crucial role in the development of various hardware, including arithmetic circuits. This paper first introduces a novel block based on a transformationbased synthesis technique from the elementary quantum gates. Then it proposes a distinctive 2×2 parity-preserving reversible quantum Vedic multiplier based on the recommended block and prior gates. In addition, further designs of Vedic multipliers are provided, encompassing 4-bit, 8-bit, and 16-bit configurations. We illustrate that our design brings superior outcomes regarding quantum cost (QC), constant inputs (CI) count, CNOT-V/V+ count, garbage outputs (GO) count, and gate count (GC) in comparison to earlier designs. This study achieves an average decrease of 23.09%, 37.51%, 37.51%, 54.89%, and 19.38% in QC, CI, GO, GC, and CNOT-V/V+ count, respectively. Furthermore, all suggested circuits undergo appraisal and validation within the IBM quantum laboratory.
Open accessCC BY-NC-ND 4.0

Keywords

  • Quantum Circuits
  • Reversible Logic
  • Multiplier
  • IBM

Suggested citation

Mojtaba Noorallahzadeh, Mohammad Mosleh (2025). A Novel and Ultra-Efficient Design of Reversible Quantum Vedic Multiplier. Quantum Information & Computation, 25(5), 552-567. https://doi.org/10.2478/qic-2025-0030

Download BibTeX

References (56)

  1. M. Saravanan and K. S. Manic (2014). “Novel reversible variable precision multiplier using reversible logic gates”. Journal of Computer Science, 10: 7, 1135.DOI: 10.3844/jcssp.2014.1135.1138Google Scholar
  2. V. Nandhini and K. Sambath (2023). “VLSI implementation of multiplier design using reversible logic gate”. Analog Integrated Circuits and Signal Processing, 115: 1, 93–100.DOI: 10.1007/s10470-023-02150-2Google Scholar
  3. M. Swathi and B. Rudra (2021). “Implementation of reversible logic gates with quantum gates”, in 2021 IEEE 11th Annual Computing and Communication Workshop and Conference (CCWC). IEEE, pp. 1557–1563.DOI: 10.1109/CCWC51732.2021.9376060Google Scholar
  4. R. Landauer (1961). “Irreversibility and heat generation in the computing process”. IBM Journal of Research and Development, 5: 3, 183–191.DOI: 10.1147/rd.53.0183Google Scholar
  5. N. Radha and M. Maheswari (2020). “An energy efficient multipliers using reversible gates”. Journal of Physics: Conference Series, 1706: 1, 012066.DOI: 10.1088/1742-6596/1706/1/012066Google Scholar
  6. H. Thapliyal and M. Srinivas (2005). “Novel reversible TSG’ gate and its application for designing components of primitive reversible/quantum ALU”, in 2005 5th International Conference on Information Communications & Signal Processing. IEEE, pp. 1425–1429.DOI: 10.1109/ICICS.2005.1689293Google Scholar
  7. N. U. Ain, S.-S. Ahmadpour, N. J. Navimipour, E. Diakina, and S. R. Kassa (2025). “Secure quantum-based adder design for protecting machine learning systems against side-channel attacks”. Applied Soft Computing, 169, 112554.DOI: 10.1016/j.asoc.2024.112554Google Scholar
  8. S.-S. Ahmadpour, D. B. Avval, M. Darbandi, N. J. Navimipour, N. U. Ain, and S. Kassa (2025). “A new quantum-enhanced approach to AI-driven medical imaging system”. Cluster Computing, 28: 3, 1–13.DOI: 10.1007/s10586-024-04852-2Google Scholar
  9. N. K. Misra, N. Pathak, B. K. Bhoi, S.-S. Ahmadpour, S. R. Kassa, and N. J. Navimipour (2025). “Nanotechnology QCA-based sub-components of processor design and application of futuristic low-power design”. Facta Universitatis, Series: Electronics and Energetics, 38: 1, 163–186.DOI: 10.2298/FUEE2501163MGoogle Scholar
  10. S. S. Ahmadpour et al. (2025). “A nano-design of a quantum-based arithmetic and logic unit for enhancing the efficiency of the future IoT applications”. AIP Advances, 15, 3.DOI: 10.1063/5.0247642Google Scholar
  11. S.-S. Ahmadpour et al. (2025). “A new median filter circuit design based on atomic silicon quantum-dot for digital image processing and IoT applications”. IEEE Internet of Things Journal.DOI: 10.1109/JIOT.2025.3553706Google Scholar
  12. H. Rasmi, M. Mosleh, N. Jafari Navimipour, and M. Kheyrandish (2024). “An ultra efficient 2:1 multiplexer using bar-shaped pattern in atomic silicon dangling bond technology”. The Journal of Supercomputing, 80: 13, 18347–18364.DOI: 10.1007/s11227-024-06104-xGoogle Scholar
  13. H. Rasmi, M. Mosleh, N. J. Navimipour, and M. Kheyrandish (2024). “Towards atomic scale quantum dots in silicon: an ultra-efficient and robust subtractor using proposed P-shaped pattern”. IEEE Transactions on Nanotechnology.DOI: 10.1109/TNANO.2024.3398560Google Scholar
  14. H. Rasmi, M. Mosleh, N. J. Navimipour, and M. Kheyrandish (2025).“Towards a scalable and efficient full-adder structure in atomic silicon dangling band technology”. Nano Communication Networks, 43, 100561.DOI: 10.1016/j.nancom.2024.100561Google Scholar
  15. M. Alharbi, G. Edwards, and R. Stocker (2023). “Reversible quantum-dot cellular automata-based arithmetic logic unit”. Nanomaterials, 13: 17, 2445.DOI: 10.3390/nano13172445Google Scholar
  16. A. N. Bahar, S. Waheed, and N. Hossain (2015). “A new approach of presenting reversible logic gate in nanoscale”. SpringerPlus, 4, 1–7.DOI: 10.1186/s40064-015-0928-4Google Scholar
  17. C. H. Bennett (1973). “Logical reversibility of computation”. IBM Journal of Research and Development, 17: 6, 525–532.DOI: 10.1147/rd.176.0525Google Scholar
  18. A. Hawash, A. Awad, and B. Abdalhaq (2020). “Reversible circuit synthesis time reduction based on subtreecircuit mapping”. Applied Sciences, 10: 12, 4147.DOI: 10.3390/app10124147Google Scholar
  19. G. Renganayaki, R. Korah, and S. Salivahanan (2018). “Design and implementation of a reversible logic circuit and its power analysis using conventional CMOS and adiabatic logic”. Journal of Computational and Theoretical Nanoscience, 15: 1, 317–323.DOI: 10.1166/jctn.2018.7090Google Scholar
  20. M. Valinataj (2017). “Novel parity-preserving reversible logic array multipliers”. The Journal of Supercomputing, 73: 11, 4843–4867.DOI: 10.1007/s11227-017-2057-zGoogle Scholar
  21. M. Valinataj, M. Mirshekar, and H. Jazayeri (2016). “Novel low-cost and fault-tolerant reversible logic adders”. Computers & Electrical Engineering, 53: 56–72.DOI: 10.1016/j.compeleceng.2016.06.008Google Scholar
  22. M. Noorallahzadeh, M. Mosleh, and K. Datta (2024). “A new design of parity-preserving reversible multipliers based on multiple-control toffoli synthesis targeting emerging quantum circuits”. Frontiers of Computer Science, 18: 6, 186908.DOI: 10.1007/s11704-023-2492-3Google Scholar
  23. M. Noorallahzadeh, M. Mosleh, N. K. Misra, and A. Mehranzadeh (2023). “A novel design of reversible quantum multiplier based on multiple-control toffoli synthesis”. Quantum Information Processing, 22: 4, 167.DOI: 10.1007/s11128-023-03918-1Google Scholar
  24. A. N. Al-Rabadi (2012). Reversible Logic Synthesis: From Fundamentals to Quantum Computing. Springer Science & Business Media.Google Scholar
  25. N. K. Misra, B. K. Bhoi, and S. R. Kassa (2024). “Utilizing a novel universal quantum gate in the design of fault-tolerant architecture”. Nano Communication Networks, 39, 100482.DOI: 10.1016/j.nancom.2023.100482Google Scholar
  26. A. Nandal, T. Vigneswaran, and A. K. Rana (2014). “Booth multiplier using reversible logic with low power and reduced logical complexity”. Indian Journal of Science and Technology, 7: 4, 525.DOI: 10.17485/ijst/2014/v7i4.15Google Scholar
  27. B. Parhami (2006). “Fault-tolerant reversible circuits”, in 2006 Fortieth Asilomar Conference on Signals, Systems and Computers. IEEE, pp. 1726–1729.DOI: 10.1109/ACSSC.2006.355056Google Scholar
  28. H. Thapliyal and N. Ranganathan (2013). “Design of efficient reversible logic-based binary and BCD adder circuits”. ACM Journal on Emerging Technologies in Computing Systems (JETC), 9: 3, 1–31.DOI: 10.1145/2491682Google Scholar
  29. M. Haghparast and M. Shams (2013). “A novel nanometric parity preserving reversible Vedic multiplier”. Journal of Basic Applied Sciences and Research, 3, 771–776.Google Scholar
  30. E. PourAliAkbar, K. Navi, M. Haghparast, and M. Reshadi, “Novel designs of fast parity-preserving reversible vedic multiplier”. 2019.DOI: 10.1007/s00034-020-01406-wGoogle Scholar
  31. Z. Ariafar and M. Mosleh (2019). “Effective designs of reversible vedic multiplier”. International Journal of Theoretical Physics, 58: 8, 2556–2574.DOI: 10.1007/s10773-019-04145-0Google Scholar
  32. M. Rashno, M. Haghparast, and M. Mosleh (2021). “Designing of parity preserving reversible vedic multiplier”. International Journal of Theoretical Physics, 60: 8, 3024–3040.DOI: 10.1007/s10773-021-04903-zGoogle Scholar
  33. M. Noorallahzadeh, M. Mosleh, S. S. Ahmadpour, J. Pal, and B. Sen (2023). “A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits”. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 36: 5, e3089.DOI: 10.1002/jnm.3089Google Scholar
  34. “Qiskit.” https://qiskit.org.Google Scholar
  35. A. Cross, “The IBM Q experience and QISKit open-source quantum computing software”, in APS March Meeting Abstracts, 2018, L58. 003.Google Scholar
  36. Y. Jaradat, M. Alia, M. Masoud, A. Mansrah, I. Jannoud, and O. Alheyasat (2023). “Roadmap for simulating quantum circuits utilising IBM’s Qiskit library: Programming approach”. The Eurasia Proceedings of Science Technology Engineering and Mathematics, 26, 624–632.DOI: 10.55549/epstem.1412445Google Scholar
  37. “BM Quantum.” https://quantum-computing.ibm.com.”Google Scholar
  38. R. P. Feynman (1986). “Quantum mechanical computers”. Foundations of Physics, 16: 6, 507–532.DOI: 10.1007/BF01886518Google Scholar
  39. T. Toffoli (1980). “Reversible computing”, in International Colloquium on Automata, Languages, and Programming. Springer, pp. 632–644.DOI: 10.1007/3-540-10003-2_104Google Scholar
  40. D. M. Miller, D. Maslov, and G. W. Dueck (2003). “A transformation based algorithm for reversible logic synthesis”, in Proceedings of the 40th Annual Design Automation Conference, pp. 318–323.DOI: 10.1145/775832.775915Google Scholar
  41. M. Noorallahzadeh and M. Mosleh (2021). “Efficient designs of reversible shift register circuits with low quantum cost”. Journal of Circuits, Systems and Computers, 30: 12, 2150215.DOI: 10.1142/S0218126621502157Google Scholar
  42. M. Noorallahzadeh and M. Mosleh (2025). “Synthesis of a reversible quantum Vedic multiplier on IBM quantum computers”. Scientific Reports, 15, 1, 18897.DOI: 10.1038/s41598-025-00494-5Google Scholar
  43. S. F. Naz and A. P. Shah (2023). “Reversible gates: A paradigm shift in computing”. IEEE Open Journal of Circuits and Systems, 4, 241–257.DOI: 10.1109/OJCAS.2023.3305557Google Scholar
  44. A. Kaltehei, M. Kurt, A. Gen ten, and S. akmak (2025). “Construction of Boolean logic gates using QFT-based adder architecture”. arXiv preprint arXiv:2504.17090.Google Scholar
  45. R. Wille, A. Chattopadhyay, and R. Drechsler (2016). “From reversible logic to quantum circuits: Logic design for an emerging technology”, in 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). IEEE, pp. 268–274.DOI: 10.1109/SAMOS.2016.7818357Google Scholar
  46. A. Barenco et al. (1995). “Elementary gates for quantum computation”. Physical Review A, 52: 5, 3457.DOI: 10.1103/PhysRevA.52.3457Google Scholar
  47. M. M. Rahman and G. W. Dueck (2013). “Properties of quantum templates”, in Reversible Computation: 4th International Workshop, RC 2012, Copenhagen, Denmark, July 2-3, 2012. Revised Papers 4. Springer, pp. 125137.Google Scholar
  48. D. Maslov, G. W. Dueck, and D. M. Miller (2005). “Toffoli network synthesis with templates”. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24: 6, 807–817.DOI: 10.1109/TCAD.2005.847911Google Scholar
  49. M. M. Rahman, A. Banerjee, G. W. Dueck, and A. Pathak (2011). “Two-qubit quantum gates to reduce the quantum cost of reversible circuit”, in 2011 41st IEEE International Symposium on Multiple-Valued Logic, IEEE, pp. 86–92.DOI: 10.1109/ISMVL.2011.56Google Scholar
  50. M. Lewandowski, N. Ranganathan, and M. Morrison (2013). “Behavioral model of integrated qubit gates for quantum reversible logic design”, in 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, pp. 194–199.DOI: 10.1109/ISVLSI.2013.6654658Google Scholar
  51. W. N. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski (2006). “Optimal synthesis of multiple output boolean functions using a set of quantum gates by symbolic reachability analysis”. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25: 9, 1652–1663.DOI: 10.1109/TCAD.2005.858352Google Scholar
  52. Y. Wang et al.(2025). “A nano-scale design of Vedic multiplier for electrocardiogram signal processing based on a quantum technology”. APL Materials, 13, 3.DOI: 10.1063/5.0241549Google Scholar
  53. M. Rashno, M. Haghparast, and M. Mosleh (2020). “A new design of a low-power reversible Vedic multiplier”. International Journal of Quantum Information, 18: 03, 2050002.DOI: 10.1142/S0219749920500021Google Scholar
  54. G. G. Kumar and V. Charishma (2012). “Design of high speed vedic multiplier using vedic mathematics techniques”. International Journal of Scientific and Research Publications, 3, 1.Google Scholar
  55. M. Haghparast and A. Bolhassani (2016). “On design of parity preserving reversible adder circuits”. International Journal of Theoretical Physics, 55: 12, 5118–5135.DOI: 10.1007/s10773-016-3133-5Google Scholar
  56. B. Sen, S. Ganeriwal, and B. K. Sikdar (2013). “Reversible logic-based fault-tolerant nanocircuits in QCA”. International Scholarly Research Notices, 2013: 1, 850267.DOI: 10.1155/2013/850267Google Scholar